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Shintaro Yamamichi

Senior Research Manager, Semiconductors, IBM Research -Tokyo, IBM Japan

Biography

Shintaro Yamamichi received his B.E., M.E. and Ph. D. degrees in electrical engineering, from Kyoto University, Japan, in 1987, 1989, and 2002, respectively. He was involved in both semiconductor and packaging process research in NEC and Renesas Electronics. He was also a visiting industrial fellow at University of California, Berkeley in 1997. In 2013, he joined IBM Research -Tokyo. In 2016 - 2022, he has been the senior manager of the Science & Technology team, leading research projects including quantum computing, AI hardware and material informatics. Currently, he is leading all the semiconductor-related research and development activities in IBM Japan.

Presentation

The digital technology evolution based on the miniaturization of transistors is expected to be accelerated by gate-all-around nano-sheet technology. In parallel, a new computation element, called Neuron, mimicking the neuro-synaptic phenomena, and another completely new element based on the quantum physics, called Qubit, are also evolving, and opening the doors for new applications. In this presentation, the current research status of three elements, Bits, Neurons, and Qubits, and their applications to the computation system will be reviewed.

Hiromasa Kaneko

Associate Professor, Department of Applied Chemistry, School of Science and Technology, Meiji University

Biography

Education history
- (2010/1 - 2010/3 Overseas research, Imperial College London, UK)
- 2009/4 - 2011/9: Ph.D. Chemical System Engineering, The University of Tokyo, Japan
- 2007/4 - 2009/4: M.S. Chemical System Engineering, The University of Tokyo, Japan
- 2005/4 - 2007/4: B.S. Chemical System Engineering, The University of Tokyo, Japan
- 2003/4 - 2005/3: B.S. Faculty of Liberal Arts, The University of Tokyo, Japan

Professional history
- 2020/4 - Now: Associate Professor
Department of Applied Chemistry, Meiji University, Japan
- 2017/4 - 2020/03: Senior Assistant Professor
Department of Applied Chemistry, Meiji University, Japan
- 2011/10 - 2017/3: Assistant Professor
Chemical System Engineering, The University of Tokyo, Japan

Presentation

The speaker's laboratory is researching on artificial intelligence and machine learning to construct mathematical models with data on various highly functional materials, to design unknown molecules, materials and processes, and to control processes based on actual process data. The researches on artificial intelligence and machine learning are completely meaningless if researchers and engineers in various fields cannot actually design new molecules, materials and processes, and control processes. Therefore, Datachemical LAB, the cloud service that enables the design and control, and artificial intelligence and machine learning calculations without programming. Using Datachemical LAB, we can design molecules, materials and processes, and control processes, based on artificial intelligence and machine learning.

Prof. Yoichiro Kurita

Specially Appointed Professor of Laboratory for Future Interdisciplinary Research of Science and Technology (FIRST), Tokyo Institute of Technology

Biography

1994 Graduated from Tokyo Institute of Technology
1996 M.S. Tokyo Institute of Technology
1996-2002 NEC (NEC Corporation)
2002-2010 NEC Electronics
2010-2012 Renesas Electronics
2012-2021 Toshiba Corporation
2021- Tokyo Institute of Technology
Ph.D. (Engineering, Tokyo Institute of Technology)

Presentation

For applications such as Artificial Intelligence (AI) and the Metaverse, which require enormous amounts of information processing and storage, conventional integrated circuits (ICs) and their implementation technologies, such as the slowdown of Moore's Law and the von Neumann bottleneck, are becoming bottlenecks. In other words, the limits of integration scale and integration density are becoming bottlenecks. In contrast, chiplet integration technology, which has the potential to optimally and scalably expand capacity by integrating many chips with different manufacturing methods, functions, and structures while maintaining the connection bandwidth between IC chips, is attracting attention as a promising method to solve such problems. On the other hand, chiplet integration technology using ?interposer?, which is currently being put to practical use, is thought to have issues in optimizing the connection density and wiring structure between chips, integration scale scalability, and cost. The Chiplet Integration Platform Consortium, led by Tokyo Institute of Technology, Osaka University, and Tohoku University, has proposed the Pillar-Suspended Bridge (PSB) structure as the minimum configuration for chip/bridge integration and its concept as MetaIC (Integrated Circuit of the Integrated Circuits). Integrated Circuits (MetaIC) as a minimum configuration for chip/bridge integration. This presentation will review the history of the technology behind chiplet integration, explain the trends and the latest status of this field, which has been progressing rapidly since the beginning of this century, and introduce the research and development activities of the consortium, including chiplet integration infrastructure, 3D integration, and optical integration.